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A System Verilog Primer

A System Verilog Primer

Par J. Bhaskar

Publié par BS Publications

English 349 pages 2021 ISBN 9789389354300
PDF
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À propos de ce livre

<div><!--block--><strong>Contents<br>1.</strong> Introduction, <strong>2.</strong> Language Elements, <strong>3.</strong> Composite Types, <strong>4.</strong> Expressions, <strong>5.</strong> Behavioral Modeling, <strong>6.</strong> Structural Modeling, <strong>7.</strong> Other Topics, <strong>8.</strong> Advanced Verification Topics, <strong>9.</strong> Assertions<br><strong>About the Author<br></strong>J. Bhasker is an Architect at eSilicon Corporation. Prior to that, he was a Distinguished Member of Technical Staff at Bell Laboratories. He has received a Meritorious Service Award from IEEE Computer Society for his technical contributions and continued leadership in the development of the EDA standards, especially the VHDL and Verilog RTL synthesis standards.</div>

Catégories

Integrated Circuits
Audience
adults
Langue
English
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